NI Academic RIO Device architecture overview

A high-level overview of the Academic RIO Device architecture and features.

Diagram of NI myRIO architecture showing RT and FPGA targets, communication subsystems (USBLAN and wireless), file system, I/O, and onboard devices

Introduction

The NI Academic RIO Device is the academic version of the NI family of reconfigurable I/O (RIO) architecture platforms including the industrial-grade CompactRIO and Single-Board RIO designed for embedded control and monitoring applications
The RIO architecture fundamentally consists of two targets offering complementary capabilities:
- Real-time (RT) processor – runs a LabVIEW VI in a similar fashion as a desktop computer, but with a real-time operating system (RTOS) to achieve deterministic (predictable) process loop timing; the RT processor also manages a flash-based file system, USB port, UART, and network adapters for both wired and wireless networking
- Field-programmable gate array (FPGA) – “runs” a LabVIEW VI by loading a bitstream configuration file (FPGA “personality”) compiled directly from the VI source code; the FPGA manages the hardware interface that connects to sensors, actuators, and peripheral devices that constitute the embedded system
In the Academic RIO Device platform, both the RT and FPGA targets physically reside on the Xilinx Zynq-7000 system-on-chip (SoC) device

Runs NI Linux Real-Time, a real-time operating system (RTOS) designed specifically for NI products
Communicates with the desktop computer’s LabVIEW development environment either through a USB-based local area network (USBLAN) or by a wireless network
Networking capabilities include TCP/IP, UDP, HTTP, secure HTTP, SMTP email, and web services
Manages an onboard flash-memory-based file system accessible with LabVIEW VIs, browser, and WebDAV
USB port supports thumb drives and webcams
The Academic RIO Device Toolkit Express VIs and low-level VIs in concert with the default Device “personality” (FPGA bitfile) provide an effortless way to perform common interfacing tasks; with this toolkit the myRIO may be viewed as a single RT target with built-in analog and digital I/O, pulse-width modulated (PWM) outputs, quadrature encoder waveform decoding, serial bus protocols (SPI and I2C), timers, and interrupt handling. All of the code examples in the NI myRIO Project Essentials Guide and the NI myRIO Vision Essentials Guide take this programming approach.

The FPGA target manages all digital input/output (DIO) devices, analog I/O (AIO), stereo audio I/O, and onboard devices (accelerometer, four LEDs, and pushbutton)
Programmed using LabVIEW FPGA; VIs use a restricted subset of LabVIEW programming constructs
Resources include:
- 4,400 slices
- 17,600 slice LUTs (look-up tables)
- 35,200 slice registers
- 60 block RAMs
- 80 DSP48s
- 32 logical interrupts
- 16 DMA channels