Make a "hello, world!"-like application to experience the advantages of multiple linked VIs running simultaneously on the FPGA target, real-time (RT) target, and desktop computer
"FPGA Main" VI -- blinks the onboard LEDs and reads the onboard pushbutton
"FPGA testbench" VI -- runs on the desktop computer for interactive development and debugging of "FPGA Main" in simulation mode prior to compiling to a bitstream file
"RT Main" VI -- runs as the RT target start-up VI; it runs "FPGA Main", interacts with its front-panel controls/indicators, and communicates with an external desktop computer via network-published shared variables
"PC Main" VI -- runs on the desktop computer as a user-friendly human-machine interface (HMI) for remote command and control of "FPGA Main" through the network
LabVIEW programming techniques for the RIO real-time (RT) processor.
Queue-based state machines excel at implementing system control, data measurement and processing, and other tasks to respond to inputs from the surrounding physical system and user interface. Popular design patterns include:
Queued state machine (QSM) for specific tasks
Queued message handler (QMH) for system-level application
Event-driven producer-consumer loops for PC-based human-machine interface (HMI) to the RT application
The RT processor supports a wide range of networking capabilities.
Use the infrastructure of the Web for machine-to-machine exchange of information. The Academic RIO Device can call Web services to retrieve information and can also host Web services to provide information to other systems.