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RIO Developer Essentials Guide for Academia

"Inter-process communication" tag

Diagram of NI myRIO architecture showing RT and FPGA targets, communication subsystems (USBLAN and wireless), file system, I/O, and onboard devices

NI Academic RIO Device architecture overview
RIO guide

A high-level overview of the Academic RIO Device architecture and features.

PC and RIO block diagram with FPGA target highlighted

Develop an FPGA VI
FPGA guide

Develop your own FPGA-targeted VI to take advantage of the unique capabilities of the FPGA target such as high-speed I/O, precision I/O timing, parallel processing, and functionality not offered by the RT processor and Academic RIO Device Toolkit default personality; you can also augment the default personality with your needed capability.

Diagram showing communication pathways three process loops on the RT target

RT inter-process communication
RT guide

Exchange data between process loops running in parallel on the RT target.

LabVIEW RT block diagram snippet: Read a single-process shared variable in one process loop that was written by another process loop

Single-process shared variable (SPSV)
RT code

A single-process shared variable (SPSV) behaves like a global variable that links deterministic and non-deterministic process loops, effectively shielding the deterministic loop from elements that contribute jitter.

Diagram showing communication pathways three process loops on the FPGA target

FPGA inter-process communication
RT guide

Exchange data between process loops running in parallel on the RT target.