Compile an FPGA VI

Code from the video: fpga_compile-fpga-vi.zip

Procedure

1. Open an existing LabVIEW project that contains an FPGA target; see Create a new FPGA project
2. Right-click the “FPGA Target”, choose “Select Execution Mode”, and then “FPGA Target”; confirm that the word “Simulation” does not appear in the FPGA Target label
3. Run the VI as you normally would
4. Select from one of these three options:
   • “Local compile server” – use the compilation tools installed on your computer
   • “Connect to a network compile server” – a remote server installed by your IT department
   • “Connect to LabVIEW FPGA Compile Cloud Service” – a subscription-based service, possibly included with your National Instruments Academic License
5. Manually rebuild the bitfile at any time by right-clicking the FPGA target “Build Specifications” and choose “Rebuild”

Important: Compiling even the simplest VI requires several minutes, therefore, you should thoroughly test and debug your VI with simulation before you commit time to compiling. See these pages to learn how to simulate an FPGA and to use the “Desktop Execution Node” as an FPGA VI testbench.

Tips

• Only one VI may be compiled at a time by the local compile server
• Multiple VIs may be compiled simultaneously with cloud-based servers
• Compilation time is at least several minutes and can be much longer (many hours) depending on the VI complexity
• The bitfile is stored in the subfolder “FPGA Bitfiles” with file type “lvbitx”
• Minor cosmetic modifications to the block diagram, e.g., adding a comment or changing the VI icon do not force a re-compile.
• Right-click on the “FPGA Target” and choose “Properties” to see available resources for the FPGA, including:
  • FPGA family, type, and speed grade
  • Resources (slices, LUTs, slice registers, block RAMs, and DSP48s)
  • Compiler information
  • Host computer/FPGA communication types
  • Number of interrupt channels
  • DMA capabilities
• Right-click on the FPGA target “Build Specification” and choose “Display Compilation Results” to see the compiler reports again

Related pages

• Create a new FPGA project
• Simulate an FPGA
• ‘Desktop Execution Node’ as an FPGA VI Testbench