Home
Quickstart Guide
Introduction RIO Academic RIO Application examples Your first RT app Your first FPGA app
Real-Time
Basic procedures System admin File system I/O monitor System controller architecture Timed loops Inter-process communication RT/Host communication RT/FPGA communication FPGA personalities Interrupts Datalogger (file I/O)
FPGA
Design flow Simulation Inter-process communication RT/host communication Derived clock domain IP blocks FPGA personality
Networking
Get connected Email Web services UDP TCP IP addresses
Site Map
Guides Code examples Procedures Tags LabVIEW block diagram elements Targets Communications All pages
Glossary How to use About
RIO Developer Essentials Guide for Academia
FPGA procedure

Simulate an FPGA VI

Debug your FPGA VI before compiling to a bitfile using execution highlighting, breakpoints, probes, and sampling probes.

https://youtu.be/0_fcLE1CYz8 (5:12)

Code from the video: fpga_simulate-fpga-vi.zip

Procedure

  1. Open an existing LabVIEW project that contains an FPGA target; see Create a new FPGA project
  2. Right-click the “FPGA Target”, choose “Select Execution Mode”, and then “Simulation (Simulated I/O)”; confirm that the word “Simulation” appears in the FPGA Target label
  3. Run the VI as you normally would
  4. Use any or all of these techniques:
    • Add temporary front-panel indicators (remember to remove them before compiling as they require FPGA fabric resources)
    • Execution highlighting
    • Breakpoints
    • Probes (can float the probe window next to the signal)
    • Sampling probes
IMPORTANT: FPGA I/O node outputs are not active during simulation; inputs are connected to random number generators. Use the “Desktop Execution” node in a desktop VI to set desired values of the FPGA I/O node outputs.

Tips

Related content

Tags:

Targets: