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"Single-Cycle Timed Loop" element

Single-Cycle Timed Loop

Screenshot of LabVIEW VI block diagram and front panel of 'FPGA Main'

Make your first FPGA application
FPGA procedure

Follow along with this step-by-step tutorial to make a "hello, world!"-like application to experience the advantages of multiple linked VIs running simultaneously on the FPGA target, real-time (RT) target, and desktop computer: (1) "FPGA Main" VI blinks the onboard LEDs and reads the onboard button; these onboard devices physically connect to the FPGA I/O pins, (2) "FPGA testbench" VI runs on the desktop computer for interactive development and debugging of "FPGA Main" in simulation mode prior to compiling to a bitstream file, (3) "RT Main" VI runs as the RT target start-up VI; it runs "FPGA Main", interacts with its front-panel controls/indicators, and communicates with an external desktop computer via network-published shared variables, and (4) "PC Main" VI runs on the desktop computer as a user-friendly human-machine interface (HMI) for remote command and control of "FPGA Main" through the network.

LabVIEW PC block diagram snippet: PC reads and writes FPGA I/O nodes in simulation mode

"Desktop Execution" node as an FPGA VI testbench
FPGA code PC code

The PC VI interacts with the FPGA VI in simulation mode to apply a test sequence as the FPGA VI input and monitor the resulting output sequence.

LabVIEW FPGA block diagram snippet: Timed loop with 10-MHz derived clock domain highlighted

Derived clock domains
FPGA code

Use a derived clock domain to effectively speed up or slow down the FPGA's 40-MHz clock for a selected portion of the FPGA block diagram.

LabVIEW FPGA block diagram snippet: VHDL code for a 4-bit Johnson counter inserted into an IP Integration node

"IP Integration" node for VHDL code reuse
FPGA code

Reuse existing and validated VHDL-based circuit functionality in the FPGA block diagram instead of developing new LabVIEW G code to implement the same functionality.

LabVIEW FPGA block diagram subpalette for Xilinx IP functions

Xilinx IP integration
FPGA code

Configure and use Xilinx IP (intellectual property) modules designed specifically for the Xilinx Zynq FPGA

LabVIEW FPGA block diagram snippet: Process Loop #1 writes an indicator, Process Loop #2 reads the indicator value with a local variable

Local variable (FPGA)
FPGA code

Use a local variable (front-panel indicator) to communicate between two parallel process loops contained within the same VI.

LabVIEW FPGA block diagrams: VI #1 writes a global variable, VI #2 reads the same global variable

Global variable (FPGA)
FPGA code

Use a global variable to communicate between two parallel process loops contained within different VIs under the same target.