Use cases

• High throughput data transfer such as audio and signal waveforms
• Exchange command and status messages through a first-in first-out (FIFO) buffer
• Lossless transfer, e.g., when every data point matters

Features

• Ideal for high-speed data streaming
• Use the “Invoke Method” function to configure, read, and write the DMA FIFO
  • Configure: request a FIFO depth and reports actual depth
  • Read: request number of elements to read; timeout says how long to wait for the FIFO to have this many values available; returns the data array and indicates the number of elements remaining to be read
  • Write: provide a data array to transfer and a timeout value to wait for sufficient space to be available to write this many elements; indicates the number of empty elements available
• Available for RT/FPGA communications, too; see Stream high-speed data with a DMA FIFO (RT)

Keep in mind

• This is streaming communication, also known as message or buffered communication
• This method has a higher CPU overhead to set up each transfer than programmatic front-panel communication, therefore it is best to transfer the largest possible block of data for each transfer
• Using the “Never arbitrate” option for the FPGA FIFO reduces its footprint by about 50 slices
• The PC may request a larger FIFO size than what is physically implemented on the FPGA:
  • The minimum FIFO depth is 1024 elements and the default is 15360 elements

LabVIEW block diagram elements

Locate these elements with "Quick Drop" (press Ctrl+Space and start typing the name); click on an icon to see more sample code that uses that element:

Example code

• Connect your Academic RIO Device to your PC using USBLAN, Ethernet, or Wi-Fi. NOTE: Not all Academic RIO Devices have Ethernet and Wi-Fi connectivity options.
• Download and unpack the fpga-pc_dma-fifo.zip (for use with NI myRIO 1900) or the NIELVISIII-fpga-pc_dma-fifo.zip (for use with NI ELVIS III) archive, and then double-click the ".lvproj" file to open the project. NOTE: This project was written for a NI myRIO 1900 or NI ELVIS III connected by USBLAN at IP address 172.22.11.2. If you are using a different IP address or another Academic RIO Device (Example: NI myRIO 1950 or NI RIO Control Module) do the following:
  • If using the NI myRIO 1950 or NI RIO Control Module start with the NI myRIO 1900 Archive.
  • Different IP address: Right-click on the "NI myRIO 1900" Device, choose "Properties", and then enter the new IP address
  • Different device:
    • Right-click on the top of the project hierarchy, select "New Targets and Devices", keep the "Existing target or device" option, and then find and select your particular device
    • Select all of the components under the "NI myRIO 1900" device: click the first one and then shift+click the last one
    • Drag the selected components to the new device
    • Right-click the "NI myRIO 1900" device and select "Remove from project"
• Connect an audio source to the Academic RIO Device “Audio In” jack and headphones or speakers to the “Audio Out” jack
  • Music from your phone is great
  • This online tone generator features sine, square, sawtooth, and triangle waveforms; adjust the volume as needed
  • Protect your hearing when using earbuds! Start with low volume!
• Open “PC Main” and check for a broken “Run” arrow indicating that the FPGA bitfile must be recompiled; if a recompile is necessary, expand the LabVIEW project hierarchy (Chassis >> FPGA Target >> Build Specifications), right-click on the “FPGA Main” build specification and select “Rebuild”
• Run “PC Main”:
  • The PC VI runs the supporting FPGA VI which samples the stereo audio input and streams audio frames (blocks of audio samples) to the PC for processing
  • The PC VI processes the entire frame at once by applying a variable gain and then streams the frames back to the FPGA
  • The FPGA VI applies the processed frames to the audio output
• Front-panel controls:
  • audio sampling rate: sets the FPGA sampling rate in kilo-samples per second
  • audio frame size: sets the number of audio samples for each DMA transfer
  • gain: gain factor applied to the audio: 0dB is no change, +dB boosts the level, and -dB cuts the level
  • minimum loop time: increase this value to artificially extend the processing loop time to illustrate the effect of buffer overflow
• Front-panel indicators:
  • depth: number of FIFO elements
  • elements remaining: number of FIFO elements yet to be transferred from FPGA to PC
  • overflow: FPGA upstream FIFO buffer is full and unable to accept a new audio input sample
  • underflow: FPGA downstream FIFO buffer is empty and unable to procduce the needed audio output sample
  • maximum loop time: The maximum allowed time to keep up with the rate at which the FPGA produces and consumes audio sampled; the value in milliseconds is frame size (S/frame) divided by sampling rate (kS/s)
  • measured loop time: displays the total time that the PC spends waiting for a new audio frame, processing it, and then transferring back to the FPGA
  • processed audio: waveform chart display of the left (blue) and right (red) processed audio signal; right-click and choose Chart History Length to change the buffer size from default of 1024 samples
  • audio sampling interval: indicates the corresponding sampling interval in microseconds according to the “audio sampling rate” control, streams the audio to the PC which applies simple processing (adjusting the gain), and then streams the processed audio back to the FPGA to be played on the audio output
• Experiment with parameters to see the effects of different frame sizes, audio sampling rates, and minimum loop time
• Increase the minimum loop time beyond the maximum allowed loop time and listen for the effects of FIFO overflow; use a sine tone to most clearly hear the noise, but you can also discern this with regular music, too.

Expected results

Developer walk-through

Outline

• Review overall structure: “FPGA Main”
  • Single process loop (conventional while-loop, perpetual)
  • Adjustable loop timer sets the sampling interval
  • Acquire left and right audio samples from the audio input as two I16 integers (16-bit signed) and join them into a single U32 integer (32-bit unsigned)
  • Write the pair of samples to the “To PC” DMA FIFO; do not check for available space (use timeout = zero) to prevent lock-up if PC is not reading the other end of the FIFO
  • Read a pair of samples as a single U32 integer from the “From PC” DMA FIFO; do not wait for data to be available (timeout = zero) to prevent blocking if PC is not writing the other end of the FIFO
  • Split into two I16 integers and write to the audio output
  • Front-panel control (loop time) and overlow/underflow indicators intended for programmatic front-panel communication with PC (or RT)
• Review overall structure: “PC Main”
  • Open a reference to the FPGA VI and run it
  • Set the depth of both DMA FIFOs
  • Processing loop:
    • Set the FPGA sampling interval and check the overflow/underflow status
    • Read a frame of audio from the FPGA (1-D array of U32 integers)
    • Split into left and right channels
    • Apply a gain factor to both channels; replace this with other audio processing filters or effects
    • Plot the processed audio
    • Assemble left and right channels back to a 1-D array of U32 integers
    • Write the frame of audio to the FPGA
    • Measure the loop time
    • Stop the loop on error or “Stop” button click
  • Close the reference to the FPGA VI and stop running it
• Create and configure the DMA FIFOs
  • Configuration dialog box
    • Name
    • Type = “Host to Target - DMA” or “Target to Host - DMA”
    • Requested number of elements
    • Data type
    • Arbitration for read
    • Number of elements per read
  • FIFO Method Node (FPGA VI)
  • Invoke Method Function (PC VI)
• Locate function palettes
  • FPGA VI
    • Split/join functions
    • FPGA I/O nodes for audio I/O
  • PC VI
    • FPGA interface functions

For more information

1. Transferring Data between the FPGA and Host (FPGA Module) (http://zone.ni.com/reference/en-XX/help/371599L-01/lvfpgaconcepts/fpga_data_transfer_overview)
   Describes direct memory access (DMA) communication and compares it to programmatic front-panel communication.
   

Related content

Tags:

• inter-target communication
• DMA
• FIFO
• streaming
• message
• application example

Targets:

• FPGA
• PC

Communications:

• streaming
• message
• inter-target
• PC-FPGA

LabVIEW VIs and block diagram elements:

• Open FPGA VI Reference
• Read-Write Control
• Invoke Method
• Close FPGA VI Reference
• FIFO Method Node
• Join Numbers
• Split Number
• Loop Timer